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| for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 1 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter features ? 80 m s p s maximum s ampling r ate ? ultra low power dissipation 59 mw/channel at 80m s p s ? 70.1 db snr at 8 mhz fi n ? 0.5 s s tartup from s leep 15 s from power down ? r educed power dissipation modes available ? internal r eference circuitry with n o e xternal components r equired ? coarse and fine gain control ? internal o ffset correction ? 1.8 v s upply v oltage ? s erial 12-bit l v d s o utput ? 14-bit l v d s o utput available up to 65m s p s ? 64 lead 9 x 9 mm s m t package t ypical a pplications ? medical imaging ? wireless infrastructure ? t est and measurement ? instrumentation pin c ompatible parts ? hmcad1101 ? hmcad1100 ? hmcad1100/01-ac specifcations are also valid for HMCAD1102 functional diagram figure 1. functional block diagram
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 2 0 - 2 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter general description HMCAD1102 is a high performance low power octal analog-to-digital converter (adc). t he adc is based on a proprietary structure and employs internal reference circuitry, a serial control interface and serial l v d s output data. data and frame synchronization output clocks are supplied for data capture at the receiver. v arious modes and confguration settings can be applied to the adc through the serial control interface ( s pi). e ach channel can be powered down independently and data format can be selected through this interface. a full chip idle mode can be set by a single external pin. r egister settings determine the exact function of this external pin. t he HMCAD1102 is designed to easily interface with feld-programmable gate arrays (fpgas) from several vendors. t he very low start up times for the HMCAD1102 allows signifcant power reduction in duty-cycled systems, by utilizing the s leep modes or power down mode when the receive path is idle. e lectrical specifcations d c e lectrical specifcations a v dd = 1.8v , d v dd = 1.8v , ov dd = 1.8v , 80 msps clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, 12 bit output, unless otherwise noted parameter description min t yp max unit dc accuracy n o missing codes guaranteed o ffset e rror o ffset error after internal digital offset correc- tion 1 l sb gain e rror 6 %fs gain matching gain matching between channels. 3sigma value at worst case conditions 0.5 %fs dnl differential nonlinearity (12-bit level) 0.2 l sb inl integral nonlinearity (12-bit level) 0.6 l sb v cm common mode voltage output v a vdd /2 analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale r ange differential input voltage range 2 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply analog s upply v oltage 1.7 1.8 2 v digital s upply v oltage digital and output driver supply voltage (up to 65 msps) 1.7 1.8 2 v digital s upply v oltage digital and output driver supply voltage (above 65 msps) 1.8 1.9 2 v ov dd s upply v oltage digital cm os input s upply v oltage 1.7 1.8 3.6 v t emperature o perating t emperature o perating free-air temperature -40 85 c for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 3 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter ac e lectrical specifcations - 80 msps a v dd = 1.8v , d v dd = 1.8v , ov dd = 1.8v , 80 msps clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, 12 bit output, unless otherwise noted parameter description min t yp max unit performance snr s ignal to noise r atio f in = 8 mhz 68.5 70.1 dbfs f in = 30 mhz 70 dbfs sinad s ignal to n oise and distortion r atio f in = 8 mhz 68 69.6 dbfs f in = 30 mhz 69.5 dbfs sfdr s purious free dynamic r ange f in = 8 mhz 74 77 dbc f in = 30 mhz 76 dbc hd2 s econd order harmonic distortion f in = 8 mhz 85 90 dbc f in = 30 mhz 90 dbc hd3 t hird order harmonic distortion f in = 8 mhz 75 77 dbc f in = 30 mhz 76 dbc enob e ffective number of bits f in = 8 mhz 11.3 bits f in = 30 mhz 11.3 bits crosstalk s ignal applied to 7 channels (f in0 ). measure - ment taken on one channel with full scale at f in1 . f in1 =8mhz, f in0 =9.9mhz 95 dbc power supply analog s upply current 173 ma digital s upply current digital and output driver supply 88 ma analog power 312 mw digital power 158 mw t otal power dissipation 470 mw power down power down mode dissipation 10 w sleep mode deep sleep mode power dissipation 56 mw sleep channel mode power dissipation with all channels in sleep channel mode (light sleep) 116 mw sleep channel s avings power dissipation savings per channel off 44 mw clock inputs max. conversion r ate 80 msps min. conversion r ate 20 msps for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 4 0 - 4 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter digital and switching specifcations a v dd = 1.8 v , d v dd = 1.8 v , ov dd = 1.8 v , unless otherwise noted parameter description min t yp max unit clock inputs duty cycle 20 80 % high compliance cm os , l v d s , l v p e cl input range, diff differential input swing 200 m v pp input range, sine differential input swing, sine wave clock input 800 m v pp input range, cm os v oltage input range cm os (clk n connected to ground) v ov dd input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ov dd -0.3 v input capacitance differential 2 pf logic inputs (cmos) v hi high level input v oltage. v ov dd 3.0 v 2 v v hi high level input v oltage. v ov dd = 1.7 v C 3.0 v 0.8 v ov dd v v li low level input v oltage. v ov dd 3.0 v 0 0.8 v v li low level input v oltage. v ov dd = 1.7 v C 3.0 v 0 0.2 v ov dd v i hi high level input leakage current 10 a i li low level input leakage current 10 a c i input capacitance 3 pf data outputs (lvds) compliance l v d s v o u t differential output voltage 350 m v v cm o utput common mode voltage 1.2 v o utput coding default/optional o ffset binary/ 2s complement timing characteristics aperture delay 0.8 ns aperture jitter <0.5 ps t s u s tart up time from power down mode and deep s leep mode to active mode. r eferences have reached 99% of fnal value. s ee section clock frequency 260 992 clock cycles s tart up time from power down mode and deep s leep mode to active mode in s. 15 s t s lpch s tart up time from s leep channel mode to active mode 0.5 s t ovr o ut of range recovery time 1 clock cycles t la t pipeline delay 14 clock cycles lvds output timing characteristics t data lclk to data delay time (excluding programmable phase shift) 250 ps t p ro p clock propagation delay. 7* t l v d s + 2.6 7* t l v d s + 3.5 7* t l v d s + 4.2 ns l v d s bit-clock duty-cycle 45 55 %lclk cycle frame clock cycle-to-cycle jitter 2.5 %lclk cycle t e dg e data rise- and fall time 20% to 80% 0.4 ns t clk e dg e clock rise- and fall time 20% to 80% 0.4 ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 5 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter a bsolute maximum r atings applying voltages to the pins beyond those specifed in t able 1 could cause permanent damage to the circuit. t able 1: a bsolute maximum r atings pin r eference pin r ating a v dd a vss -0.3 v to +2.3 v d v dd d vss -0.3 v to +2.3 v ov dd a vss -0.3 v to +3.9 v a vss / d vss d vss / a vss -0.3 v to +0.3 v analog inputs and outputs a vss -0.3 v to +2.3 v clkx a vss -0.3 v to +3.9 v l v d s outputs d vss -0.3 v to +2.3 v digital inputs d vss -0.3 v to +3.9 v t able 2: maximum t emperature r atings o perating t emperature -40 to +85 c s torage t emperature -60 to +150 c maximum junction t emperature 110 c t hermal r esistance ( r th) 25 c/w s oldering profle qualifcation j- st d-020 es d s ensivity hbm class 1c es d s ensivity cdm class iii e l e c trost a t ic sens i t i ve d ev ic e o b serve ha n dli n g p re cau t i ons s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 6 0 - 6 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter pin c onfguration and description figure 2. package diagram t able 3: pin descriptions pin n umber function description 49, 50, 57 a v dd analog power supply, 1.8 v 60 ov dd digital cm os inputs supply voltage 3, 6, 9, 37, 40, 43, 46 a vss analog ground 1 ip1 positive differential input signal, channel 1 2 i n 1 n egative differential input signal, channel 1 4 ip2 positive differential input signal, channel 2 5 i n 2 n egative differential input signal, channel 2 7 ip3 positive differential input signal, channel 3 8 i n 3 n egative differential input signal, channel 3 10 ip4 positive differential input signal, channel 4 11 i n 4 n egative differential input signal, channel 4 38 ip5 positive differential input signal, channel 5 39 i n 5 n egative differential input signal, channel 5 41 ip6 positive differential input signal, channel 6 42 i n 6 n egative differential input signal, channel 6 44 ip7 positive differential input signal, channel 7 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 7 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 3: pin descriptions pin n umber function description 45 i n 7 n egative differential input signal, channel 7 47 ip8 positive differential input signal, channel 8 48 i n 8 n egative differential input signal, channel 8 0, 12, 14, 36 d vss digital ground 35 d v dd digital and i/ o power supply, 1.8 v 13 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the s pi power down feature 15 d1p l v d s channel 1, positive output 16 d1 n l v d s channel 1, negative output 17 d2p l v d s channel 2, positive output 18 d2 n l v d s channel 2, negative output 19 d3p l v d s channel 3, positive output 20 d3 n l v d s channel 3, negative output 21 d4p l v d s channel 4, positive output 22 d4 n l v d s channel 4, negative output 27 d5p l v d s channel 5, positive output 28 d5 n l v d s channel 5, negative output 29 d6p l v d s channel 6, positive output 30 d6 n l v d s channel 6, negative output 31 d7p l v d s channel 7, positive output 32 d7 n l v d s channel 7, negative output 33 d8p l v d s channel 8, positive output 34 d8 n l v d s channel 8, negative output 23 fclkp l v d s frame clock (1x), positive output 24 fclk n l v d s frame clock (1x), negative output 25 lckp l v d s bit clock, positive output 26 lck n l v d s bit clock, negative output 51 n c n ot connected 52 t p t est pin, leave unconnected or connect to ground 53 v cm common mode output pin, 0.5*a v dd 54 n c n ot connected 55 n c n ot connected 56 n c n ot connected 58 clkp positive differential input clock 59 clk n n egative differential input clock. 61 c sn chip select enable. active low 62 s da t a s erial data input 63 s clk s erial clock input 64 resetn r eset s pi interface. active low for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 8 0 - 8 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter serial i nterface t he HMCAD1102 confguration registers can be accessed through a serial interface formed by the pins s da t a (serial interface data), s clk (serial interface clock) and c sn (chip select, active low). t he following occurs when c sn is set low: ? s erial data are shifted into the chip ? at every rising edge of s clk, the value present at s da t a is latched ? s da t a is loaded into the register every 24th rising edge of s clk multiples of 24-bit words data can be loaded within a single active c sn pulse. if more than 24 bits are loaded into s da t a during one active c sn pulse, only the frst 24 bits are kept. t he excess bits are ignored. e very 24-bit word is divided into two parts: ? t he frst eight bits form the register address ? t he remaining 16 bits form the register data acceptable s clk frequencies are from 20 mhz down to a few hertz. duty-cycle does not have to be tightly controlled. t iming diagram figure 4 shows the timing of the serial port interface. t able 5 explains the timing variables used in fgure 4. c s n s c l k s d a t a t s t h t c s t c h i t h i t l o t c k t c h a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 figure 3. s erial port interface timing t able 5: serial port i nterface timing defnitions parameter description minimum v alue unit t cs s etup time between c sn and s clk 8 ns t ch hold time between c sn and s clk 8 ns t hi s clk high time 20 ns t lo s clk low time 20 ns t ck s clk period 50 ns t s data setup time 5 ns t h data hold time 5 ns start up i nitialization as part of the HMCAD1102 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. make sure that the supply voltages are properly settled before the start up initialization is being performed. r eset can be done in one of two ways: 1. by applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the rst bit high. internal registers are reset to default values when this bit is set. t he rst bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down cycling can be done in one of two ways: 1. by applying a high-going pulse (minimum 20 ns) on the pd pin (asynchronous). 2. by cycling the s pi register 0fhex pd bit to high (reg value 0200hex) and then low (reg value 0000hex). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 9 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t iming diagrams t l v d s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n+14 n+ 1 5 a nalog input a dc c l oc k lcl k p lclk n f clk n f clk p d xx < 1: 0> n - 2 n - 2 d 1 0 d 1 1 t pr o p figure 4. l v d s timing 12 bit output, dd r mode d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 n n n n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n + 1 4 n+15 a nalog input a dc c l oc k lclk n lcl k p f clk n f clk p d xx < 1: 0> t pr o p t l v d s figure 5. l v d s timing 14 bit output, dd r mode for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 10 0 - 10 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t l v d s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n+14 n+15 a nalog input a dc c l oc k lclk n lcl k p f clk n f clk p d xx < 1: 0> n - 2 n - 2 d 1 0 d 1 1 t pr o p figure 6. l v d s timing 12 bit output, s d r mode t l v d s t l v d s /2 dx x < 1: 0> t dat a lclk p lclk n figure 7. l v d s data timing, dd r mode serial r egister map t able 6: summary of functions supported by the serial interface n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex rst s elf-clearing software reset inactive x 00 pd_ch <8:1> channel-specifc power- down inactive x x x x x x x x 0f sleep go to sleep-mode inactive x pd go to power-down inactive x pd_pin_cfg <1:0> confgures the pd pin for sleep-modes pd pin confgured for power-down mode x x ilvds_lclk <2:0> l v d s current drive programmability for lclkp and lclk n pins 3.5 ma drive x x x 11 ilvds_ frame<2:0> l v d s current drive programmability for fclkp and fclk n pins 3.5 ma drive x x x ilvds_dat <2:0> l v d s current drive programmability for output data pins 3.5 ma drive x x x for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 11 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 6: summary of functions supported by the serial interface n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex en_lvds_term e nables internal termination for l v d s buffers t ermination disabled x 12 term_lclk <2:0> programmable termination for lclk n and lclkp buffers t ermination disabled 1 x x x term_frame <2:0> programmable termination for fclk n and fclkp buffers t ermination disabled 1 x x x term_dat <2:0> programmable termination for output data buffers t ermination disabled 1 x x x invert_ch <8:1> s waps the polarity of the analog input pins ipx is positive input x x x x x x x x 24 en_ramp e nables a repeating full- scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_ pat e nables the mode wherein the output toggles between two defned codes inactive 0 x 0 single_custom_ pat e nables the mode wherein the output is a constant specifed code inactive 0 0 x bits_custom1 <13:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the l s b inactive x x x x x x x x x x x x x x 26 bits_custom2 <13:0> bits for the second code of the dual custom pattern inactive x x x x x x x x x x x x x x 27 gain_ch1 <3:0> programmable gain for channel 1 0db gain x x x x 2a gain_ch2 <3:0> programmable gain for channel 2 0db gain x x x x gain_ch3 <3:0> programmable gain for channel 3 0db gain x x x x gain_ch4 <3:0> programmable gain for channel 4 0db gain x x x x gain_ch5 <3:0> programmable gain for channel 5 0db gain x x x x 2b gain_ch6 <3:0> programmable gain for channel 6 0db gain x x x x gain_ch7 <3:0> programmable gain for channel 7 0db gain x x x x gain_ch8 <3:0> programmable gain for channel 8 0db gain x x x x phase_ddr <1:0> controls the phase of lclk output relative to data 90 degrees x x 42 pat_deskew e nables deskew pattern mode inactive 0 x 45 pat_sync e nables sync pattern mode inactive x 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 12 0 - 12 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 6: summary of functions supported by the serial interface n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex btc_mode binary twos complement format for adc output data s traight offset binary x 46 msb_frst s erialized adc output data comes out with m s b frst l s b-frst output x en_sdr e nable s d r output mode. lclk becomes a 12x/14x input clock dd r output mode x fall_sdr r ising edge of lclk comes in the middle of the data window in s d r mode r ising edge x 1 perfm_cntrl <2:0> adc performance control n ominal x x x 50 ext_vcm_bc <1:0> v cm buffer driving strength control n ominal x x lvds_pd_mode controls l v d s power down mode high z mode x 52 lvds_num_bits s ets the number of l v d s output bits 12 bit x 53 lvds_advance advance l v d s data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay l v d s data bits and frame clock by one clock cycle inactive x 0 fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 55 clk_freq <1:0> input clock frequency 65 mhz x x 56 description of serial r egisters software r eset n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex rst s elf-clearing software reset inactive x 0 s etting the rst register bit to 1, resets all internal registers including the rst register bit itself. power-down modes n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex pd_ch <8:1> channel-specifc power-down. inactive x x x x x x x x 0f sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg <1:0> confgures the pd pin for sleep-modes. pd pin confgured for power-down mode x x lvds_pd_mode controls l v d s power down mode high z mode x 52 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 13 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t here are several ways to power down HMCAD1102, from sleep modes with short start up time to full power down with extremely low power dissipation. t here are two sleep modes, both with the l v d s clocks (fclk, lclk) running, such that the synchronization with the receiver is maintained. t he frst is a light sleep mode ( pd_ch<8:1> ) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. s etting pd_ch for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 14 0 - 14 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 7: lv ds output drive strength for lcl k, f cl k and data ilvds_*<2:0> l v d s drive strength 000 3.5 ma (default) 001 2.5 ma 010 1.5 ma 011 0.5 ma 100 7.5 ma 101 6.5 ma 110 5.5 ma 111 4.5 ma lv ds i nternal t ermination programmability n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex en_lvds_ term e nables internal termination for l v d s buffers t ermination disabled x 12 term_lclk <2:0> programmable termination for lclk n and lclkp buffers t ermination disabled 1 x x x term_frame <2:0> programmable termination for fclk n and fclkp buffers t ermination disabled 1 x x x term_dat <2:0> programmable termination for dxp and dx n buffers t ermination disabled 1 x x x t he off-chip load on the l v d s buffers may represent a characteristic impedance that is not perfectly matched with the pcb traces. t his may result in refections back to the l v d s outputs and loss of signal integrity. t his effect can be mitigated by enabling an internal termination between the positive and negative outputs of each l v d s buffer. internal termination mode can be selected by setting the en_lvds_term bit to 1. o nce this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. t able 8 shows how the internal termination of the l v d s buffers are programmed. t he values are typical values and can vary by up to 20% from device to device and across temperature. t able 8: lv ds output i nternal t ermination for lcl k, f cl k and data term_*<2:0> l v d s internal t ermination 0 t ermination disabled 1 280 10 165 11 100 100 125 101 82 110 67 111 56 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 15 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter a nalog i nput i nvert n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex invert_ch <8:1> s waps the polarity of the analog input pins ipx is positive input x x x x x x x x 24 t he ipx pin represents the positive analog input pin, and i n x represents the negative (complementary) input. s etting the bits marked invert_ch <8:1> (individual control for each channel) causes the inputs to be swapped. i n x would then represent the positive input, and ipx the negative input. lv ds t est patterns n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex en_ramp e nables a repeating full- scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_ pat e nables the mode wherein the output toggles between two defned codes inactive 0 x 0 single_ custom_pat e nables the mode wherein the output is a constant specifed code inactive 0 0 x bits_custom1 <13:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the l s b inactive x x x x x x x x x x x x x x 26 bits_custom2 <13:0> bits for the second code of the dual custom pattern inactive x x x x x x x x x x x x x x 27 pat_deskew e nables deskew pattern mode inactive 0 x 45 pat_sync e nables sync pattern mode inactive x 0 t o ease the l v d s synchronization setup of HMCAD1102, several test patterns can be set up on the outputs. n ormal adc data are replaced by the test pattern in these modes. s etting en_ramp to 1 sets up a repeating full-scale ramp pattern on all data outputs. t he ramp starts at code zero and is increased 1l s b every clock cycle. it returns to zero code and starts the ramp again after reaching the full-scale code. a constant value can be set up on the outputs by setting single_custom_pat to 1, and programming the desired value in bits_custom1 <13:0>. in this mode, bits_custom1 <13:0> replaces the adc data at the output, and is controlled by l s b-frst and m s b-frst modes in the same way as normal adc data are. t he device may also be made to alternate between two codes by programming dual_custom_pat to 1. t he two codes are the contents of bits_custom1 <13:0> and bits_custom2 <13:0>. t wo preset patterns can also be selected: 1. deskew pattern: s et using pat_deskew , this mode replaces the adc output with 01010101010101 (two l s bs removed in 12 bit mode). 2. s ync pattern: s et using pat_sync , the normal adc word is replaced by a fxed 11111110000000 word (111111000000 in 12 bit mode) n ote: o nly one of the above patterns should be selected at the same time. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 16 0 - 16 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter programmable gain n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex gain_ch1 <3:0> programmable gain for channel 1 0 db gain x x x x 2a gain_ch2 <3:0> programmable gain for channel 2 0 db gain x x x x gain_ch3 <3:0> programmable gain for channel 3 0 db gain x x x x gain_ch4 <3:0> programmable gain for channel 4 0 db gain x x x x gain_ch5 <3:0> programmable gain for channel 5 0 db gain x x x x 2b gain_ch6 <3:0> programmable gain for channel 6 0 db gain x x x x gain_ch7 <3:0> programmable gain for channel 7 0 db gain x x x x gain_ch8 <3:0> programmable gain for channel 8 0 db gain x x x x HMCAD1102 includes a purely digital programmable gain option in addition to the full-scale control. t he programmable gain of each channel can be individually set using four bits, indicated as gain_chx <3:0> for channel x. t he gain setting is coded in binary from 0 db to 12 db, as shown in t able 9. t able 9: gain setting for channels 1-8 gain_chx <3:0> channel x gain s etting 0000 0 db 0001 1 db 0010 2 db 0011 3 db 0100 4 db 0101 5 db 0110 6 db 0111 7 db 1000 8 db 1001 9 db 1010 10 db 1011 11 db 1100 12 db 1101 do not use 1110 do not use 1111 do not use for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 17 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter lv ds c lock programmability and data output modes n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex phase_ddr <1:0> controls the phase of lclk output relative to data. 90 degrees. x x 42 btc_mode binary twos complement format for adc output data. s traight offset binary. x 46 msb_frst s erialized adc output data comes out with m s b frst. l s b-frst output. x en_sdr e nable s d r output mode. lclk becomes a 12x input clock. dd r output mode. x fall_sdr controls whether the lclk rising or falling edge comes in the middle of the data window when operating in s d r mode. r ising edge of lclk comes in the middle of the data window. x 1 t he output interface of HMCAD1102 is normally a dd r interface, with the lclk rising and falling edge transitions in the middle of alternate data windows. t he phase for lclk can be programmed relative to the output frame clock and data bits using phase_ddr <1:0>. t he lclk phase modes are shown in fgure 9. t he default timing is identical to setting phase_ddr <1:0>=10. f cl k n f cl k p lclk p lcl k n d xx < 1: 0> f cl k n f cl k p lclk p lclk n d xx < 1: 0> f clk n f clk p lclk p lclk n d x x < 1 :0 > f clk n f clk p l cl k p lclk n d x x < 1 :0 > p h ase _ ddr<1: 0>='00' (270 deg) p h ase _ ddr<1: 0>='10' (90 deg) p h ase _ ddr<1: 0>='01' (180 deg) p ha s e _ddr< 1 : 0 >=' 1 1 ' ( 0 de g ) figure 8. phase programmability modes for lclk t he device can also be made to operate in s d r mode by setting the en_sdr bit to 1. t he bit clock (lclk) is output at 12x times the input clock in this mode, two times the rate in dd r mode. depending on the state of fall_sdr , lclk may be output in either of the two manners shown in figure 10. as can be seen in figure 10, only the lclk rising (or falling) edge is used to capture the output data in s d r mode. t he s d r mode is not recommended beyond 40 m s p s because the lclk frequency becomes very high. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 18 0 - 18 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter f cl k n f cl k p lcl k p lclk n d xx < 1: 0> f clk n f clk p lclk p lclk n d x x < 1 :0 > e n_ s dr='1' , f a ll_ s dr_'0 ' e n _s dr='1' , f a l l _ s d r _ ' 1 ' figure 9. sdr interface modes t he default data output format is offset binary. t wos complement mode can be selected by setting the btc_mode bit to 1 which inverts the m s b. t he frst bit of the frame (following the rising edge of fclkp) is the l s b of the adc output for default settings. programming the msb_frst mode results in reverse bit order, and the m s b is output as the frst bit following the fclkp rising edge. n umber of serial output bits and lv ds output timing n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex lvds_num_bits s ets the number of l v d s output bits 12 bit x 53 lvds_advance advance l v d s data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay l v d s data bits and frame clock by one clock cycle inactive x 0 t he adc channels have 13 bits of resolution. t here are two options for the serial l v d s outputs, 12 bits or 14 bits, selected by setting lvds_num_bits to 0 or 1, respectively. in 12 bits mode, the l s b bit from the adcs are removed in the output stream. in 14 bit mode, a 0 is added in the l s b position. power down mode must be activated after or during a change in the number of output bits. t o ease timing in the receiver when using multiple adc chips, HMCAD1102 has the option to adjust the timing of the output data and the frame clock. t he propagation delay with respect to the adc input clock can be moved one l v d s clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. s ee fgure 11 for details. n ote that lclk is not affected by lvds_delay or lvds_advance settings. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 19 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 a d c c l oc k lcl k p lclk n f cl k p f clk n d xx < 1: 0> d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 f cl k p f clk n d xx < 1: 0> d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 f c lk p f cl k n dx x < 1 :0 > lvds _ d e l ay = ' 1 ' : l v ds _ a d v a n c e = ' 1 ' : def a u l t : t l vd s d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 t l vd s t l v d s t pr o p t pr o p t pr o p figure 10. lvds output timing adjustment full-scale c ontrol n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 55 t he full-scale voltage range of HMCAD1102 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. t his leads to a maximum range of 10% adjustment. t able 10 shows how the register settings correspond to the full-scale range. n ote that the values for full-scale range adjustment are approximate. t he dac is, however, guaranteed to be monotonous. t he full-scale control and the programmable gain features differ in two major ways: 1. t he full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. t he programmable gain feature has much coarser gain steps and larger range than the full-scale control. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 20 0 - 20 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 10: r egister v alues with c orresponding c hange in full-scale r ange fs_cntrl<5:0> full-scale range adjustment 111111 9.70% 111110 9.40% 100001 0.30% 100000 0% 011111 ?0.3% 000001 ?9.7% 000000 ?10% t o optimize start up time, a register is provided where the input clock frequency can be set. s ome internal circuitry have start up times that are clock frequency independent. default counter values are set to accommodate these start up times at the maximum clock frequency. t his will lead to increased start up times at low clock frequency. s etting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better ft the actual start up time, such that the start up time will be reduced. t he start up times from power down mode and deep s leep mode are changed by this register setting. t able 11: c lock frequency settings clk_freq <1:0> clock frequency range s tartup delay (clock cycles) s tartup delay (s) 0 0 50 - 80 mhz 992 12.4 - 19.8 0 1 32.5 - 50 mhz 640 12.8 - 19.7 1 0 20 - 32.5 mhz 420 12.9 - 21 1 1 15 - 20 mhz 260 13 - 17.3 performance c ontrol n ame description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address in hex perfm_cntrl <2:0> adc performance control n ominal x x x 50 ext_vcm_bc <1:0> v cm buffer driving strength control n ominal x x t here are two registers that impact performance and power dissipation. t he perfm_cntrl register adjusts the performance level of the adc core. if full performance is required, the nominal setting must be used. t he lowest code can be used in situations where power dissipation is critical and performance is less important. for most conditions the performance at the minimum setting will be similar to nominal setting. however, only 11 bit performance can be expected at worst case conditions. t he power dissipation savings shown in table 12 are only approximate numbers for the adc current alone. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 21 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter t able 12: performance c ontrol settings perfm_cntrl<2:0> analog power dissipation 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) n ominal 001 do not use 010 do not use 011 do not use t he ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the v cm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the v cm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. t able 13: e xternal c ommon mode v oltage buffer driving strength ext_vcm_bc <1:0> vcm buffer driving strength [a] max current sinked/sourced from v cm pin with < 50 m v voltage change. 00 o ff ( v cm foating) 01 (default) 6.5 10 70 11 140 t heory of operation HMCAD1102 is an 8-channel, high-speed, cm os adc. t he outputs from each channel are serialized to 12 or 14 bits and sent out on a single pair of pins in l v d s format. all eight channels of HMCAD1102 operate from one clock input, which can be differential or single ended. t he sampling clocks for each of the eight channels are generated from the clock input using a carefully matched clock buffer tree. t he 12x clock required for the serializer is generated internally from fclk using a phase-locked loop (pll). a 6x and 1x clock are also output in l v d s format, along with the data to enable easy data capture. HMCAD1102 uses internally generated references. t he differential reference value is 1 v . t his results in a differential input of ?1 v to correspond to the zero code of the adc, and a differential input of +1 v to correspond to the full- scale code (code 8191). t he adc employs a pipelined converter architecture. e ach stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at 12-bit level. HMCAD1102 operates from two sets of supplies and grounds. t he analog supply and ground set is identifed as a v dd and a vss , while the digital set is identifed by d v dd and d vss . r ecommended usage analog input t he analog input to HMCAD1102 is a switched capacitor track-and-hold amplifer optimized for differential operation. o peration at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. t he v cm pin provides a voltage suitable as common mode voltage reference. t he internal buffer for the v cm voltage can be switched off, and driving capabilities can be changed programming the ext_ vcm_bc <1:0> register. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 22 0 - 22 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter figure 11. input confguration figure 12 shows a simplifed drawing of the input network. t he signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 o hm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. t he resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. dc-coupling figure 13 shows a recommended confguration for dc-coupling. n ote that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ext output should be used as reference to set the common mode voltage. figure 12. dc coupled input t he input amplifer could be inside a companion chip or it could be a dedicated amplifer. s everal suitable single ended to differential driver amplifers exist in the market. t he system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with HMCAD1102 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in fgure 13 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 14 shows a recommended confguration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. t he bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. t his type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. figure 13. transformer coupled input if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. t his could reduce the adc performance. t o avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in fgure 16 can be used. figure 14. ac coupled input figure 15 shows ac-coupling using capacitors. r esistors from the cm_ext output, r cm, should be used to bias the differential input signals to the correct voltage. t he series capacitor, ci, form the high- for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 23 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. n ote that s tart up t ime from s leep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc are not effectively terminated at the signal source, the input network of fgure 16 can be used. t he confguration in fgure 16 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below n yquist. figure 15. alternative input network v alues of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. t his capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. clock input and jitter considerations t ypically high-speed adcs use both clock edges to generate internal timing signals. in HMCAD1102 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. t he input clock can be supplied in a variety of formats. t he clock pins are ac-coupled internally, hence a wide common mode voltage range is accepted. differential clock sources such as l v d s , l v p e cl or differential sine wave can be connected directly to the input pins. for cm os inputs, the clk n pin should be connected to ground, and the cm os clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least 0.8 v pp. n o additional confguration is needed to set up the clock source format. t he quality of the input clock is extremely important for high-speed, high-resolution adcs. t he contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1. snr jitter = 20 log (2 ? in ? t ) (1) where f in is the signal frequency, and t is the total rms jitter measured in seconds. t he rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. t his can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. t he jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with l v d s or l v p e cl clock with fast edges. cm os and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 24 0 - 24 HMCAD1102 v03.0611 octal 12-bit 80 msps a /d co nverter outline drawing t able 14: dimensions s ymbol millimeter inch min t yp max min t yp max a 0.9 0.035 a1 0 0.01 0.05 0 0.0004 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 re f. 0.008 re f. b 0.2 0.25 0.3 0.008 0.01 0.012 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc d2 5 5.2 5.4 0.197 0.205 0.213 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 1.3 0.05 g 0.24 0.42 0.6 0.0096 0.0168 0.024 package i nformation part number package body material lead finish msl [1] package marking [2] HMCAD1102 r oh s -compliant low s tress injection molded plastic 100% matte s n level 2a had1102 xxxx [1] m s l, peak t emp: t he moisture sensitivity level rating classifed according to the j e d e c industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx |
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